AD9517-4ABCPZ-RL7 데이터 시트보기 (PDF) - Analog Devices

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AD9517-4ABCPZ-RL7

12-Output Clock Generator with Integrated 1.6 GHz VCO

Analog Devices 

AD9517-4

TIMING DIAGRAMS

CLK

tCLK

tPECL

tLVDS

tCMOS

Figure 2. CLK/CLK to Clock Output Timing, DIV = 1

DIFFERENTIAL

80%

20%

LVPECL

tRP

tFP

Figure 3. LVPECL Timing, Differential

Data Sheet

DIFFERENTIAL

80%

20%

LVDS

tRL

tFL

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

20%

CMOS

10pF LOAD

tRC

tFC

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

Rev. E | Page 16 of 80

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