AD73422BB-80 데이터 시트보기 (PDF) - Analog Devices
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AD73422BB-80 Datasheet PDF : 36 Pages
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AD73422
Parameter
Min Typ Max Units Test Conditions
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single-Ended
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
PGA = 6 dB
Total Harmonic Distortion at 0 dBm0
PGA = 6 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk, DAC-to-ADC
1.578
–2.85
3.156
3.17
1.0954
–6.02
2.1909
0
1.2
–0.85 +0.4
± 0.1
62.5 77
–80
–85
–85
–90
+0.85
–62.5
V p-p
dBm
V p-p
dBm
V p-p
dBm
V p-p
dBm
V
dB
dB
dB
dB
dB
dBm0
dB
DAC-to-DAC
Power Supply Rejection
Group Delay4, 5
Output DC Offset2, 7
Minimum Load Resistance, RL2, 8
Single-Ended4
Differential
Maximum Load Capacitance, CL2, 8
Single-Ended4
Differential
–77
dB
–100
dB
–65
dB
25
50
–20 +20
µs
µs
+60 mV
600
Ω
600
Ω
500 pF
100 pF
PGA = 6 dB
Max Output = (1.578/1.25) × VREFCAP
PGA = 6 dB
Max Output = 2 × ((1.578/1.25) × VREFCAP)
PGA = 6 dB
PGA = 6 dB
REFOUT Unloaded
1.0 kHz, 0 dBm0; Unloaded
1.0 kHz, +3 dBm0 to –50 dBm0
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Level: AGND;
DAC Output Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
DAC1 Output Level: AGND;
DAC2 Output Level: 1.0 kHz, 0 dBm0
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Interpolator Bypassed
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance4
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
DVDD – 0.8
0
–10
12
DVDD V
0.8 V
+10 µA
24
pF
DVDD – 0.4
0
–10
DVDD V
0.4 V
+10 µA
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
POWER SUPPLIES
AVDD
DVDD
IDD10
3.0
3.6 V
3.0
3.6 V
See Table I
NOTES
1 Operating temperature range is as follows: –20°C to +85°C; therefore, TMIN = –20°C and TMAX = +85°C.
2 Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3 At input to sigma-delta modulator of ADC.
4 Guaranteed by design.
5 Overall group delay will be affected by the sample rate and the external digital filtering.
6 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 1011)/DMCLK.
7 Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
8 At VOUT output.
9 Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB pream-
plifier bypassed and input gain of 0 dB.
10Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
REV. 0
–3–
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