82C50A 데이터 시트보기 (PDF) - Intersil

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82C50A

CMOS Asynchronous

Intersil 

82C50A

AC Test Circuit

OUTPUT FROM

DEVICE UNDER TEST

V1

R1

TEST

POINT

C1 (NOTE)

NOTE: Includes stay and jig capacitance.

TEST CONDITION DEFINITION TABLE

IOH

IOL

V1

R1

C1

-2.5mA

+2.5mA

1.7V

520Ω

100pF

Timing Waveforms

AC Testing Input, Output Waveform

INPUT

VIH + 0.4V

1.5V

VIL - 0.4V

OUTPUT

VOH

1.5V

VOL

AC Testing: All input signals must switch between VIL -0.4V and

VIH +0.4V. Input rise and fall times are driven at 1ns/V.

tXH

(27)

XTAL1

tXL

(28)

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

FIGURE 3. EXTERNAL CLOCK INPUT

FIGURE 4. AC TEST POINTS

XTAL1

(31) tBHD

(30) tBLD

BAUD OUT

(÷1)

(31) tBHD

(30)

tBLD

BAUD OUT

(÷2)

(30)

tBLD

BAUD OUT

(÷3)

(30)

tBLD

BAUD OUT

(÷N, N > 3)

N

(29)

tHW (33)

(33)

tHW

(31)

tBHD

(31)

tBHD

tLW (32)

tLW (32)

tHW

(33)

tLW

(32)

tHW = (N - 2) XTAL1 CYCLES

(33)

(32)

tLW = 2XTAL1 CYCLES

NOTE: tBLD (÷1) is the only spec measure from XTL1 falling edge. All other tBLD’s and tBHD’s are measured from XTAL1 rising edge.

FIGURE 5. BAUDOUT TIMING

20

FN2958.5

August 24, 2006

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