PALCE20V8H-25 데이터 시트보기 (PDF) - Lattice Semiconductor

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PALCE20V8H-25

EE CMOS 24-Pin Universal Programmable Array Logic

Lattice Semiconductor 

Dedicated Input in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The

feedback signal is an adjacent I/O pin.

Combinatorial I/O in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available

to the OR gate. The eighth product term is used to enable the output buffer. The signal at the

I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used

as an input.

Combinatorial I/O in a Registered Device

The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available

to the OR gate. The eighth product term is used as the output enable. The feedback signal is the

corresponding I/O signal.

Table 1. Macrocell Configuration

Cell

SG0 SG1 SL0X Configuration

Devices

Emulated

Cell

SG0 SG1 SL0X Configuration

Devices

Emulated

Device Uses Registers

Device Uses No Registers

0

1

0

Registered Output

PAL20R8, 20R6,

20R4

1

0

0

Combinatorial

Output

PAL20L2, 18L4,

16L6, 14L8

0

1

1

Combinatorial

I/O

PAL20R6, 20R4

1

0

1

Input

PAL20L2, 18L4, 16L6

1

1

1

Combinatorial

I/O

PAL20L8

PALCE20V8 Family

5

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