FX802J 데이터 시트보기 (PDF) - CML Microsystems Plc
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FX802J Datasheet PDF : 14 Pages
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Timing Information
CHIP SELECT
SERIAL CLOCK
t CSE
COMMAND DATA
76 54 3 2 10
MSB
LSB
REPLY DATA
ADDRESS/COMMAND
BYTE
Logic level is not important
t CSOFF
t NXT
t NXT
t CK
76 54 3 2 10
FIRST DATA BYTE
7 654 3 2 10
MSB
LSB
FIRST REPLY DATA BYTE
7 6 543 2 10
LAST DATA BYTE
7 6 543 2 10
LAST REPLY DATA BYTE
t CSH
t HIZ
Fig.5 “C-BUS” Timing Information
NOT TO SCALE
“C-BUS” Timing – Figure 5
Direct Access Timing – Figure 6
Parameter
Min.
Max.
Unit
Parameter
Min.
Typ
Max.
Unit
abc
t
CSE
2.0 4.0 8.0 –
µs
t
CSH
4.0 4.0 8.0 –
µs
t
HIZ
–
–
– 2.0
µs
tCSOFF
2.0 4.0 8.0 –
µs
tNXT
4.0 8.0 16.0 –
µs
t
CK
2.0 4.0 8.0 –
µs
t
1.0
–
CH
t
1.0
–
CL
t
450
–
SU
tH
600
–
t
–
–
PCO
tSU + tH = Data True Time
–
µs
–
µs
–
ns
–
ns
750
ns
Notes
(1) Minimum Timing Values
(a) For all commands except “Read Data” and “Write Data” commands.
(b) For “Read Data” and “Write Data” commands when no “Speech Store” or “Speech Play” commands are active.
(c) For “Read Data” and “Write Data” commands when “Speech Store” or “Speech Play” commands are active.
(2) Depending on the command, 1 or 2 bytes of Command Data are transmitted to the peripheral MSB (bit7) first, LSB
(bit0) last. Reply Data is read from the peripheral MSB (bit7) first, LSB (bit0) last.
(3) To allow for differing µController serial interface formats “C-BUS” compatible ICs are able to work with either polarity
Serial Clock pulses.
(4) Data sent from the µController is clocked into the FX802 on the rising edge of the Serial Clock pulses. Reply Data
sent from the FX802 to the µController is clocked into the µController when the Serial Clock is “high.”
(5) Loaded commands are acted upon at the end of each command.
Direct Access
ENCODER TIMING
ENCODER CLOCK
t CH
ENCODER DATA
BITS OUT
t PCO
Data Clocked
t CL
Fig.6 Codec Direct Access Timing
DECODER TIMING
DECODER CLOCK
t CH
t CL
DECODER DATA
BITS IN
Data Clocked
t SU
tH
Data True Time
NOT TO SCALE
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