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AD5222

Increment/Decrement Dual Digital Potentiometer

Analog Devices 

AD5222–SPECIFICATIONS (VDD = 3 V ؎ 10% or 5 V ؎ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40؇C < TA < +85؇C,

unless otherwise noted.)

Parameter

Symbol Condition

Min Typ1 Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL2

Resistor Nonlinearity2

Nominal Resistor Tolerance

Resistance Temperature Coefficient

Wiper Resistance3

Nominal Resistance Match

R-DNL

R-INL

∆R

RAB/∆T

RW

∆R/RO

RWB, VA = NC

RWB, VA = NC

VAB = VDD, Wiper = No Connect, TA = 25°C

VAB = VDD, Wiper = No Connect

IW = VDD/R, VDD = 3 V or 5 V

CH 1 to 2, VAB = VDD, TA = 25°C

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Resolution

N

Integral Nonlinearity4

Differential Nonlinearity4

INL

INL

DNL

RAB = 10 kΩ, 50 kΩ, or 100 kΩ

RAB = 1 MΩ

Voltage Divider Temperature Coefficient ∆VW/∆T

Full-Scale Error

VWFSE

Code = 40H

Code = 7FH

Zero-Scale Error

VWZSE

Code = 00H

RESISTOR TERMINALS

Voltage Range5

Capacitance6 A, B

Capacitance6 W

Common-Mode Leakage

VA, B, W

CA, B

CW

ICM

f = 1 MHz, Measured to GND, Code = 40H

f = 1 MHz, Measured to GND, Code = 40H

VA = VB = VW

DIGITAL INPUTS AND OUTPUTS

Input Logic High

VIH

Input Logic Low

VIL

Input Current

IIL

Input Capacitance6

CIL

VDD = 5 V/3 V

VDD = 5 V/3 V

VIN = 0 V or 5 V

–1

±1/4 +1

LSB

–1

±0.4 +1

LSB

–30

+30 %

–35

ppm/°C

45 100 Ω

0.2 1

%

7

Bits

–1

±1/4 +1

LSB

–2

±1/2 +2

LSB

–1

±1/4 +1

LSB

20

ppm/°C

–1 –0.5 +0 LSB

0

0.5 1

LSB

VSS

VDD V

45

pF

60

pF

1

nA

2.4/2.1

5

V

0.8/0.6 V

±1

µA

pF

POWER SUPPLIES

Power Single-Supply Range

Power Dual-Supply Range

Positive Supply Current

Negative Supply Current

Power Dissipation7

Power Supply Sensitivity

VDD RANGE

VDD/SS RANGE

IDD

ISS

PDISS

PSS

VSS = 0 V

VIH = 5 V or VIL = 0 V

VSS = –2.5 V, VDD = +2.7 V

VIH = 5 V or VIL = 0 V, VDD = 5 V

2.7

5.5 V

± 2.3

±2.7 V

15 40

µA

15 40

µA

150 400 µW

0.002 0.05 %/%

DYNAMIC CHARACTERISTICS6, 8, 9

Bandwidth –3 dB

Total Harmonic Distortion

VW Settling Time

Resistor Noise Voltage

BW_10K

BW_50K

BW_100K

BW_1M

THDW

tS

eN_WB

RAB = 10 kΩ, Code = 40H

RAB = 50 kΩ, Code = 40H

RAB = 100 kΩ, Code = 40H

RAB = 500 kΩ, Code = 40H

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz

RAB = 10 kΩ, ± 1 LSB Error Band

RWB = 5 kΩ, f = 1 kHz

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts)6, 10

Input Clock Pulsewidth

tCH, tCL

Clock Level High or Low

30

CS to CLK Setup Time

tCSS

20

CS Rise to CLK Hold Time

tCSH

20

U/D to Clock Fall Setup Time

tUDS

10

U/D to Clock Fall Hold Time

tUDH

30

DACSEL to Clock Fall Setup Time

tDSS

20

DACSEL to Clock Fall Hold Time

tDSH

30

MODE to Clock Fall Setup Time

tMDS

20

MODE to Clock Fall Hold Time

tMDH

40

1000

180

78

7

0.005

2

14

kHz

kHz

kHz

kHz

%

µs

nV√Hz

ns

ns

ns

ns

ns

ns

ns

ns

ns

NOTES

1Typicals represent average readings at 25°C, VDD = 5 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.

3Wiper resistance is not measured on the RAB = 1 MΩ models.

4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.

5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6Guaranteed by design and not subject to production test.

7PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

8Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

9All dynamic characteristics use VDD = 5 V.

10See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level

of 1.5 V. Switching characteristics are measured using both VDD = 5 V or VDD = 3 V.

Specifications subject to change without notice.

–2–

REV. 0

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