CY7C68034-56LTXI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C68034-56LTXI Datasheet PDF : 40 Pages
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CY7C68033/CY7C68034
Sequence Diagram
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram [27]
FIFOADR
SLRD
SLCS
FLAGS
DATA
SLOE
tSFA
tFAH
t=0
tRDpwl tRDpwh
t=2
t=3
tSFA
tFAH
T=0
tRDpwl tRDpwh
tRDpwl tRDpwh
tRDpwl tRDpwh
T=2
T=3
T=4
T=5
T=6
tXFLG
tXFLG
Data (X)
Driven
tXFD
N
tOEon
tOEoff
N
tOEon
tXFD
N+1
tXFD
N+2
tXFD
N+3
tOEoff
t=1
t=4
T=1
T=7
Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram
FIFO POINTER
SLOE
N
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
SLOE
N+3
FIFO DATA BUS Not Driven
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 17 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■ At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
■ At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
■ At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum deactive pulse width of
tRDpwh. If SLCS is used then, SLCS must be in asserted with
SLRD or before SLRD is asserted (that is the SLCS and SLRD
signals must both be asserted to start a valid read condition).
■ The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of tXFD from the activating edge of SLRD. In Figure 17, data N
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is
incremented.
Note
27. Dashed lines denote signals with programmable polarity.
Document Number: 001-04247 Rev. *J
Page 32 of 40
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