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EP2AGX260DH29I6ES

Arria II Device Handbook

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Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices

Boundary-Scan Description Language Support

11–7

1 If you do not use the IEEE Std. 1149.1 circuitry in Arria II devices, permanently

disable the circuitry to ensure that you do not inadvertently enable it when it is not

required.

Table 11–5 lists the pin connections necessary for disabling the IEEE Std. 1149.1

circuitry in Arria II devices.

Table 11–5. Pin Connections Necessary for Disabling IEEE Std. 1149.1 Circuitry for Arria II

Devices

JTAG Pins

TMS

TCK

TDI

TDO

TRST

Connection for Disabling

Arria II GX Devices

Arria II GZ Devices

VCC supply of Bank 8C

VCCPD supply of Bank 1A

GND

VCC supply of Bank 8C

VCCPD supply of Bank 1A

Leave Open

Not available

GND

Boundary-Scan Description Language Support

The boundary-scan description language (BSDL), a subset of VHDL, provides a

syntax that allows you to describe the features of an IEEE Std. 1149.6 BST-capable

device that can be tested. You can test software development systems, then use the

BSDL files for test generation, analysis, and failure diagnostics.

f For more information about BSDL files for IEEE Std. 1149.6-compliant Arria II GX

devices, refer to the IEEE 1149.6 BSDL Files page on the Altera® website.

f For more information about BSDL files for IEEE Std. 1149.1-compliant Arria II GZ

devices, refer to the IEEE 1149.1 BSDL Files page on the Altera website.

f

You can also generate BSDL files (pre-configuration and post-configuration) for

Arria II devices with the Quartus® II software version 9.1 and later. For the procedure

to generate BSDL files using the Quartus II software, refer to Generating BSDL Files in

Quartus II.

December 2013 Altera Corporation

Arria II Device Handbook Volume 1: Device Interfaces and Integration

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