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Arria II Device Handbook

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1–12

Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Auto-Calibrating External Memory Interfaces

■ I/O structure enhanced to provide flexible and cost-effective support for different

types of memory interfaces

■ Contains features such as OCT and DQ/DQS pin groupings to enable rapid and

robust implementation of different memory standards

■ An auto-calibrating megafunction is available in the Quartus II software for

DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RLDRAM II memory interface

PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration

feature to calibrate based on the changes of process, voltage, and temperature

(PVT).

f For the maximum clock rates supported in Altera's FPGA devices, refer to the

External Memory Interface Spec Estimator online tool.

f For more information about the external memory interfaces support, refer to the

External Memory Interfaces in Arria II Devices chapter.

Nios II

■ Arria II devices support all variants of the NIOS® II processor

■ Nios II processors are supported by an array of software tools from Altera and

leading embedded partners and are used by more designers than any other

configurable processor

Configuration Features

■ Configuration

■ Supports active serial (AS), passive serial (PS), fast passive parallel (FPP), and

JTAG configuration schemes.

■ Design Security

■ Supports programming file encryption using 256-bit volatile and non-volatile

security keys to protect designs from copying, reverse engineering, and

tampering in FPP configuration mode with an external host (such as a MAX® II

device or microprocessor), or when using the AS, FAS, or PS configuration

scheme

■ Decrypts an encrypted configuration bitstream using the AES algorithm, an

industry standard encryption algorithm that is FIPS-197 certified and requires

a 256-bit security key

Arria II Device Handbook Volume 1: Device Interfaces and Integration

July 2012 Altera Corporation

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