datasheetbank_Logo
전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

EP2AGX190EH25C4N 데이터 시트보기 (PDF) - Unspecified

부품명
상세내역
제조사
EP2AGX190EH25C4N
ETC
Unspecified 
EP2AGX190EH25C4N Datasheet PDF : 380 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
1–10
Chapter 1: Overview for the Arria II Device Family
Arria II Device Architecture
The Quartus® II software allows you to take advantage of MLABs, M9K, and
M144K memory blocks by instantiating memory using a dedicated megafunction
wizard or by inferring memory directly from VHDL or Verilog source code.
Table 1–7 lists the Arria II device memory modes.
Table 1–7. Memory Modes for Arria II Devices
Port Mode
Single Port
Simple Dual Port
True Dual Port
Port Width Configuration
x1, x2, x4, x8, x9, x16, x18, x32, x36, x64, and x72
x1, x2, x4, x8, x9, x16, x18, x32, x36, x64, and x72
x1, x2, x4, x8, x9, x16, x18, x32, and x36
DSP Resources
Fulfills the DSP requirements of 3G and Long Term Evolution (LTE) wireless
infrastructure applications, video processing applications, and voice processing
applications
DSP block input registers efficiently implement shift registers for finite impulse
response (FIR) filter applications
The Quartus II software includes megafunctions you can use to control the mode
of operation of the DSP blocks based on user-parameter settings
You can directly infer multipliers from the VHDL or Verilog HDL source code
I/O Features
Contains up to 20 modular I/O banks
All I/O banks support a wide range of single-ended and differential I/O
standards listed in Table 1–8.
Table 1–8. I/O Standards Support for Arria II Devices
Type
I/O Standard
Single-Ended I/O
LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X
Differential I/O
SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS) (1), and
RSDS
Note to Table 1–8:
(1) BLVDS is only available for Arria II GX devices.
Supports programmable bus hold, programmable weak pull-up resistors, and
programmable slew rate control
For Arria II devices, calibrates OCT or driver impedance matching for
single-ended I/O standards with one OCT calibration block on the I/O banks
listed in Table 1–9.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]