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IN74ALS74

Dual D Flip-Flop with Set and Reset

Integral Corp. 

Dual D Flip-Flop with Set and Reset

TECHNICAL DATA

IN74ALS74

Each of the two independent positive edge-triggered flip-flops in

this circuit has individual Data, Clock, Set and Reset inputs, and

complementary Q and Q outputs.

• Switching specifications at 50 pF

• Switching specifications guaranteed over full temperature and VCC

range

• Functionally and pin-for-pin compatible with Schottky and LS TTL

counterpart

• Improved AC performance over LS74 at approximately half the

power

ORDERING INFORMATION

IN74ALS74N Plastic

IN74ALS74D SOIC

TA = -10° to 70° C

for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

PIN 14 =VCC

PIN 7 = GND

FUNCTION TABLE

Inputs

Outputs

Set Reset Clock Data Q Q

LH

X

XH L

HL

X

XLH

L

L

X

X

H*

H*

HH

HH L

HH

L

L

H

HH

L

X No Change

HH

H

X No Change

HH

X No Change

*Both outputs will remain high as long as Set

and Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

X = don’t care

1

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