XRT91L80IB(2005-03) 데이터 시트보기 (PDF) - Exar Corporation

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XRT91L80IB
(Rev.:2005-03)

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

xr

REV. P1.0.4

HARDWARE CONTROL

NAME

LEVEL

RLOOPS

LVTTL

RLOOPP

LVTTL

DLOOP

LVTTL

LPTIME_JA

LVTTL

LPTIME_NO_JA

LVTTL

PRELIMINARY

XRT91L80

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

TYPE

I

I

I

I

I

PIN

DESCRIPTION

C10 Serial Remote Loopback

Hardware Mode The serial remote loopback mode intercon-

nects the receive serial input data to the transmit serial output

data. If serial remote loopback is enabled, the 4-bit parallel

transmit input data is ignored while the 4-bit parallel receive

output data is maintained.

"Low" = Disabled

"High" = Serial Remote Loopback Mode Enabled

This pin is provided with an internal active pull-down.

NOTE: DLOOP and RLOOPS can be enabled simultaneously

to achieve a dual loopback diagnostic feature.

A11 Parallel Remote Loopback

Hardware Mode The parallel remote loopback mode allows the

input serial data stream to pass through the clock and data

recovery circuit and loopback at the parallel interface to the

serial output port. The 4-bit parallel transmit input data is

ignored while the 4-bit parallel receive output data is main-

tained.

"Low" = Disabled

"High" = Parallel Remote Loopback Mode Enabled

This pin is provided with an internal active pull-down.

NOTE: DLOOP and RLOOPS should be disabled when

RLOOPP is enabled.

B6 Digital Loopback

Hardware Mode The digital loopback mode interconnects the

4-bit parallel transmit input data and TxCLK to the 4-bit parallel

receive output data and RxCLK respectively while maintaining

the transmit serial output data. If digital loopback is enabled,

the receive serial input data is ignored.

"Low" = Disabled

"High" = Digital Loopback Mode Enabled

This pin is provided with an internal active pull-down.

NOTE: DLOOP and RLOOPS can be enabled simultaneously

to achieve a dual loopback diagnostic feature.

C6 Loop Timing Mode With Jitter Attenuation

The LPTIME_JA pin must be set "High" in order to select the

recovered receive clock as the reference source for the de-jitter

PLL.

"Low" = Disabled

"High" = Enabled

This pin is provided with an internal active pull-down.

P2 Loop Timing Mode With No Jitter Attenuation

When the loop timing mode is activated the external reference

clock to the input of the CMU is replaced with the 1/16th or the

1/32nd of the high-speed recovered receive clock from the

CDR.

"Low" = Disabled

"High" = Loop timing Activated

This pin is provided with an internal active pull-down.

5

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