XRT91L80IB(2005-03) 데이터 시트보기 (PDF) - Exar Corporation

부품명

상세내역

제조사

XRT91L80IB
(Rev.:2005-03)

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

XRT91L80

PRELIMINARY

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

TABLE OF CONTENTS

xr

REV. P1.0.4

GENERAL DESCRIPTION .................................................................................................1

APPLICATIONS ...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF XRT91L80 ...................................................................................................................................... 1

FEATURES ......................................................................................................................................................2

PRODUCT ORDERING INFORMATION ..................................................................................................2

FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW).......................................................................................................... 3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS ..........................................................................................................4

SERIAL MICROPROCESSOR INTERFACE............................................................................................................4

HARDWARE CONTROL.....................................................................................................................................5

TRANSMITTER SECTION ..................................................................................................................................6

RECEIVER SECTION.........................................................................................................................................8

POWER AND GROUND ....................................................................................................................................9

NO CONNECTS.............................................................................................................................................10

JTAG ..........................................................................................................................................................11

1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12

1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12

1.2 INPUT CLOCK REFERENCE ......................................................................................................................... 12

TABLE 1: REFERENCE FREQUENCY OPTIONS (NORMALMODE/FEC) ................................................................................................ 12

1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 12

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 12

2.0 RECEIVE SECTION .............................................................................................................................13

2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13

FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13

2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14

2.3 LOSS OF SIGNAL .......................................................................................................................................... 14

2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 14

FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 14

2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 15

FIGURE 6. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 15

2.6 RECEIVE PARALLEL OUTPUT DATA TIMING ............................................................................................ 15

FIGURE 7. RECEIVE PARALLEL OUTPUT TIMING .............................................................................................................................. 15

TABLE 2: RECEIVE PARALLEL OUTPUT DATA TIMING SPECIFICATIONS.............................................................................................. 15

2.7 DISABLE RECEIVE OUTPUT DATA UPON LOS .......................................................................................... 15

2.8 TRI-STATE RECEIVE OUTPUT DATA .......................................................................................................... 15

3.0 TRANSMIT SECTION ..........................................................................................................................16

3.1 TRANSMIT PARALLEL INTERFACE ............................................................................................................ 16

FIGURE 8. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................... 16

3.2 TRANSMIT PARALLEL INPUT DATA TIMING .............................................................................................. 17

FIGURE 9. TRANSMIT PARALLEL INPUT TIMING ................................................................................................................................ 17

TABLE 3: TRANSMIT PARALLEL INPUT DATA TIMING SPECIFICATIONS ............................................................................................... 17

3.3 TRANSMIT FIFO ............................................................................................................................................. 17

3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 17

3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 18

FIGURE 10. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 18

3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 18

FIGURE 11. TRANSMIT FIFO AND SYSTEM INTERFACE .................................................................................................................... 19

3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 20

TABLE 4: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS .............................................................................................. 20

FIGURE 12. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO .......................................................................................... 21

3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 21

FIGURE 13. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER .................................................................................................. 21

3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 22

FIGURE 14. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 22

4.0 DIAGNOSTIC FEATURES ...................................................................................................................23

4.1 SERIAL REMOTE LOOPBACK ...................................................................................................................... 23

FIGURE 15. SERIAL REMOTE LOOPBACK......................................................................................................................................... 23

4.2 PARALLEL REMOTE LOOPBACK ................................................................................................................ 23

I

Share Link: