MC100EP33DG(2016) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100EP33DG Datasheet PDF : 11 Pages
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MC10EP33, MC100EP33
RESET 1
CLK 2
CLK 3
8 VCC
R
7Q
B4
6Q
VBB 4
5 VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK*, CLK*
Reset*
VBB
Q, Q
ECL Clock Inputs
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnected,
floating open.
* Pins will default LOW when left open.
Table 2. TRUTH TABLE
CLK CLK RESET
Q
Q
X
X
Z
Z
Z
L
L
H
F
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8 NB
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 kW
NA
> 4 kV
> 200 V
> 2 kV
Pb-Free Pkg
Level 1
Level 3
Level 1
UL−94 V−0 @ 0.125 in
91 Devices
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