X5643 데이터 시트보기 (PDF) - Xicor -> Intersil

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X5643

CPU Supervisor with 64Kbit SPI EEPROM

Xicor -> Intersil 

X5643/X5645

Figure 3. VTRIP Programming Sequence Flow Chart

VTRIP Programming

New VCC Applied =

Old VCC Applied + Error

Execute

Reset VTRIP

Sequence

Set VCC = VCC Applied =

Desired VTRIP

Execute

Set VTRIP

Sequence

Apply 5V to VCC

Decrement VCC

(VCC = VCC - 10mV)

New VCC Applied =

Old VCC Applied - Error

Execute

Reset VTRIP

Sequence

NO

RESET pin

goes active?

YES

Error ≥ Emax

Emax = Maximum Desired Error

Measured VTRIP -

Desired VTRIP

Error > Emax

Error < Emax

DONE

REV 1.1.1 3/5/01

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