X5328P-2.7 데이터 시트보기 (PDF) - Intersil
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X5328P-2.7 Datasheet PDF : 21 Pages
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Serial Input Timing
CS
SCK
SI
tLEAD
tSU
tH
MSB IN
X5328, X5329
tRI
tCS
tLAG
tFI
LSB IN
SO
High Impedance
Serial Output Timing
2.7-5.5V
Symbol
Parameter
Min.
Max.
Unit
fSCK
Clock Frequency
0
2
MHz
tDIS
Output Disable Time
250
ns
tV
Output Valid from Clock Low
250
ns
tHO
Output Hold Time
0
ns
tRO(3)
Output Rise Time
100
ns
tFO(3)
Output Fall Time
100
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
tCYC
tWH
tLAG
tV
tHO
tWL
tDIS
SO
MSB Out
MSB–1 Out
LSB Out
SI
ADDR
LSB IN
14
FN8132.1
October 17, 2005
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