X28C512J-12 데이터 시트보기 (PDF) - Intersil

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X28C512J-12

5V, Byte Alterable EEPROM

Intersil 

Block Diagram

X28C512, X28C513

A7-A15

X Buffers

Latches and

Decoder

512Kbit

EEPROM

Array

A0-A6

Y Buffers

Latches and

Decoder

CE

OE

WE

VCC

VSS

Control

Logic and

Timing

I/O Buffers

and Latches

I/O0-I/O7

Data Inputs/Outputs

2

FN8106.1

September 29, 2005

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