W83697UF 데이터 시트보기 (PDF) - Winbond

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W83697UF

WINBOND LPC I/O

Winbond 

W83697UF/W83697UG

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

Bit 0:

URCPWD

0 Power down

1 No Power down

Reserved

URBPWD

0 Power down

1 No Power down

URAPWD

0 Power down

1 No Power down

PRTPWD

0 Power down

1 No Power down

FDCPWD

0 Power down

1 No Power down

CR23 (Default 0xfe)

Bit [7:1]: Reserved.

Bit 0:

IPD (Immediate Power Down).

When set to 1, it will put the whole chip into power down mode immediately.

CR24 (Default 0s1000ss)

Bit 7: Flash ROM I/F Address Segment (000F0000h ~ 000FFFFFh) enable/disable

0 Enable

1 Disable

Bit 6: CLKSEL(Enable 48Mhz)

0 The clock input on Pin 1 should be 24 MHz.

The clock input on Pin 1 should be 48 MHz.

1

The corresponding power-on setting pin is SOUTB (pin 61).

Bit [5:4]: ROM size select

00 1M

01 2M

10 4M

11 Reserved

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