CXA3017R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA3017R

Decoder/Driver/Timing Generator for Color LCD Panels

Sony Semiconductor 

CXA3017R

Item

Symbol

Conditions

Min. Typ. Max. Unit

Serial transfer block

ts0

LOAD setup time, activated by the rising edge of SCLK. 150

ns

(See Fig. 6.)

Data setup time

ts1

DATA setup time, activated by the rising edge of SCLK. 150

ns

(See Fig. 6.)

th0

LOAD hold time, activated by the rising edge of SCLK. 150

ns

(See Fig. 6.)

Data hold time

th1

DATA hold time, activated by the rising edge of SCLK. 150

ns

(See Fig. 6.)

Minimum pulse

width

tw1L

tw1H

tw2

SCLK pulse width. (See Fig. 6.)

SCLK pulse width. (See Fig. 6.)

LOAD pulse width. (See Fig. 6.)

156

ns

156

ns

1

µs

– 20 –

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