UPD78323G 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD78323G

16/8-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD78323, 78324

1.2 PINS OTHER THAN PORTS (1/2)

Pin Name

I/O

RTP0 to RTP7 Output

NMI

Input

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

TI

TXD

RXD

SO

SI

SB0

SB1

Input

Input

Output

Input

Output

Input

Input

/output

SCK

Input

/output

Input

AD0 to AD7 /output

A8 to A15

TO00

TO01

TO02

TO03

TO10

TO11

RD

WR

TAS

TMD

Output

Output

Output

WDTO Output

ASTB

Output

Function

Realtime output port which generates pulses in synchronization with the trigger signal

transmitted from the realtime pulse unit (RPU).

Nonmaskable interrupot request input capable of specifying the effective at the rising or

falling edge by a mode register.

External interrupt request input capable of specifying the effective edgy by a mode

register.

External count clock input to timer 1 (TM1)

Serial data output of asynchronous serial interface (UART)

Serial data input of asynchronous serial interface (UART)

Serial data output of clock synchronous serial interface in 3-wire mode

Serial data input of clock synchronous serial interface in 3-wire mode

Serial data output of clock synchronous serial interface in SBI mode

Dual-

Function Pin

P00 to P07

P20

P21

P22

P23

P24

P25

P26

P27/TI

P27/INTP6

P30

P31

P32/SB0

P33/SB1

P32/SO

P33/SI

Serial clock input/output of clock synchronous serial interface

P34

Multiplexed address/data bus for external memory expansion

P40 to P47

Address bus for external memory expansion

Pulse output from the realtime pulse unit

Strobe signal output generated for external memory read operation

P50 to P57

P80

P81

P82

P83

P84

P85

P90

Strobe signal output generated for external memory write operation

P91

P92

Control signal output generated for access to turbo access manager µPD71P301Note

P93

Signal output indicating that the watchdog timer has generated a nonmascable

––

interrupt.

Timing signal output generated for externally latching the address information output from

––

pins AD0 to AD7 in order to access the external memory.

Note Maintenance product

12

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