UPD4991ACX 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD4991ACX

4-BIT PARALLEL I/O CALENDAR CLOCK

NEC => Renesas Technology 

µPD4991A

PIN FUNCTION

• WE ..................... Write control pin (input).

The contents of the data bus are written to an address specified by the address bus at the

rising edge of WE.

• OE ..................... Read control pin (input).

While OE = “L” level, the contents specified by the address bus are read to the data bus.

• A3 to A0 .............. Address bus pins (input).

These pins specify an internal address of the µPD4991A.

• D3 to D0 ............. Data bus pin (I/O).

These pins constitute a bidirectional bus.

• CS1, CS2 ........... Chip select pins (input).

When CS1 = “L” and CS2 = “H”, data can be transferred between the µPD4991A and the CPU.

• TP1 .................... Timing pulse pin (output) (N-ch open-drain).

Outputs an alarm coincidence signal.

• TP2 .................... Timing pulse pin (output) (N-ch open-drain).

Outputs an interval timer signal.

• XIN ...................... Crystal oscillation signal pin (input).

Inverter input for oscillation.

• XOUT ................... Crystal oscillation signal pin (output).

Inverter output for oscillation.

• VDD ..................... Positive power supply pin.

• VSS ..................... GND pin.

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