MC10EL52, MC100EL52
D1
D2
D
CLK 3
8 VCC
7Q
6Q
CLK 4
5 VEE
Figure 1. Logic Diagram and Pinout Assignment
Table 1. TRUTH TABLE
D*
CLK*
Q
L
Z
L
H
Z
H
Z = LOW to HIGH Transition
* Pin will default low when left open.
Table 2. PIN DESCRIPTION
PIN
FUNCTION
D, D
CLK, CLK
Q, Q
VCC
VEE
ECL Data Input
ECL Clock Input
ECL Data Output
Positive Supply
Negative Supply
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI ≤ VCC
VI ≥ VEE
8
V
−8
V
6
V
−6
50
mA
100
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
−40 to +85
−65 to +150
190
130
°C
°C
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
TSSOP−8
TSSOP−8
41 to 44
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
TSSOP−8
41 to 44 ±5%
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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