AD871JD 데이터 시트보기 (PDF) - Analog Devices
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AD871JD Datasheet PDF : 16 Pages
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AD871
THEORY OF OPERATION
The AD871 is implemented using a 4-stage pipelined multiple
flash architecture. A differential input track-and-hold amplifier
(THA) acquires the input and converts the input voltage into a
differential current. A 4-bit approximation of the input is made
by the first flash converter, and an accurate analog representa-
tion of this 4-bit guess is generated by a digital-to-analog con-
verter. This approximation is subtracted from the THA output
to produce a remainder, or residue. This residue is then sampled
and held by the second THA, and a 4-bit approximation is gen-
erated and subtracted by the second stage. Once the second
THA goes into hold, the first stage goes back into track to ac-
quire a new input signal. The third stage provides a 3-bit ap-
proximation/subtraction operation, and produces the final
residue, which is passed to a final 4-bit flash converter. The 15
output bits from the four flash converters are accumulated in
the correction logic block, which adds the bits together using the
appropriate correction algorithm, to produce the 12-bit output
word. The digital output, together with overrange indicator, is
latched into an output buffer to drive the output pins.
The additional THA inserted in each stage of the AD871 archi-
tecture allows pipelining of the conversion. In essence, the con-
verter is simultaneously converting multiple inputs serially,
processing them through the converter chain. This means that
while the converter is capable of capturing a new input sample
every clock cycle, it actually takes three clock cycles for the con-
version to be fully processed and appear at the output. This
“pipeline delay” is often referred to as latency, and is not a con-
cern in most applications; however, there are some cases where
it may be a consideration. For example, some applications call
for the A/D converter to be placed in a high speed feedback
loop, where its input is servoed to provide a desired result at the
digital output (e.g., offset calibration or zero restoration in video
applications). In these cases the 3 clock cycle delay through
the pipeline must be accounted for in the loop stability calcula-
tions. Also, because the converter is simultaneously working on
three conversions, major disruptions to the part (such as a large
glitch on the supplies or reference) may corrupt three data
samples. Finally, there will be a minimum clock rate below
which the THA droop corrupts the signal in the pipeline. In the
case of the AD871, this minimum clock rate is 10 kHz.
The high impedance differential inputs of the AD871 allow a
variety of input configurations (see Applying the AD871). The
AD871 converts the voltage difference between the VINA and
VINB pins. For single-ended applications, one input pin (VINA or
VINB) may be grounded, but even in this case the differential in-
put can provide a performance boost: for example, for an input
coming from a coaxial cable, VINB can be tied to the shield
ground, allowing the AD871 to reject shield noise as common
mode. The high input impedance of the device minimizes exter-
nal driving requirements and allows the user to externally select
the appropriate termination impedance for the application.
The AD871 clock circuitry uses both edges of the clock in its in-
ternal timing circuitry (see Specifications page for exact timing
requirements.) The AD871 samples the analog input on the ris-
ing edge of the clock input. During the clock low time (between
the falling edge and rising edge of the clock) the input THA is in
track mode; during the clock high time it is in hold. System dis-
turbances just prior to the rising edge of the clock may cause the
part to acquire the wrong value, and should be minimized.
While the part uses both clock edges for its timing, jitter is only
a significant issue for the rising edge of the clock (see CLOCK
INPUT section).
APPLYING THE AD871
ANALOG INPUTS
The AD871 features a high impedance differential input that
can readily operate on either single-ended or differential input
signals. Table I summarizes the nominal input voltage span for
both single-ended and differential modes, assuming a 2.5 V ref-
erence input.
Table I. Input Voltage Span
Single-Ended
Differential
VINA
+1 V
–1 V
+0.5 V
–0.5 V
VINB
GND
GND
–0.5 V
+0.5 V
VINA–VINB
+1 V (Positive Full Scale)
–1 V (Negative Full Scale)
+1 V (Positive Full Scale)
–1 V (Negative Full Scale)
Figure 10 shows an approximate model for the analog input cir-
cuit. As this model indicates, when the input exceeds 1.6 V
(with respect to AGND), the input device may saturate, causing
the input impedance to drop substantially and significantly re-
ducing the performance of the part. Input compliance in the
negative direction is somewhat larger, showing virtually no deg-
radation in performance for inputs as low as –1.9 V.
VINA OR VINB
؎1V
+5V
1.75mA
+1.6V
5pF
–1.9V
1.75mA
–5V
AD871
Figure 10. AD871 Equivalent Analog Input Circuit
Figure 11 illustrates the effect of varying the common-mode
voltage of a –0.5 dB input signal on total harmonic distortion.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–1
0
1
CM INPUT VOLTAGE – Volts
Figure 11. AD871 Total Harmonic Distortion vs. CM Input
Voltage, fIN = 1 MHz, FS = 5 MSPS
REV. A
–9–
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