ADG707BRUZ 데이터 시트보기 (PDF) - Analog Devices
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ADG707BRUZ Datasheet PDF : 12 Pages
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ADG706/ADG707
Table I. ADG706 Truth Table
A3 A2 A1 A0 EN ON Switch
X
X
X
X
0
NONE
0
0
0
0
1
1
0
0
0
1
1
2
0
0
1
0
1
3
0
0
1
1
1
4
0
1
0
0
1
5
0
1
0
1
1
6
0
1
1
0
1
7
0
1
1
1
1
8
1
0
0
0
1
9
1
0
0
1
1
10
1
0
1
0
1
11
1
0
1
1
1
12
1
1
0
0
1
13
1
1
0
1
1
14
1
1
1
0
1
15
1
1
1
1
1
16
X = Don’t Care
Table II. ADG707 Truth Table
A2 A1 A0
X
X
X
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
X = Don’t Care
EN ON Switch Pair
0
NONE
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
VDD
VSS
IDD
ISS
GND
S
D
AX
EN
VD (VS)
RON
∆RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
VINH
IINL(IINH)
CS (OFF)
TERMINOLOGY
Most positive power supply potential
Most negative power supply in a dual-supply
application. In single-supply applications, this
should be tied to ground at the device.
Positive supply current
Negative supply current
Ground (0 V) reference
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input
Active high device enable
Analog voltage on terminals D, S
Ohmic resistance between D and S
ON Resistance match between any two channels,
i.e., RONmax – RONmin
Flatness is defined as the difference between the
maximum and minimum value of ON resistance
as measured over the specified analog signal
range.
Source leakage current with the Switch “OFF”
Drain leakage current with the Switch “OFF”
Channel leakage current with the Switch “ON”
Maximum input voltage for Logic “0”
Minimum input voltage for Logic “1”
Input current of the digital input
“OFF” Switch Source Capacitance. Measured
with reference to ground.
CD (OFF)
CD, CS (ON)
CIN
tTRANSITION
tON (EN)
tOFF (EN)
tOPEN
Charge
Injection
OFF Isolation
Crosstalk
Bandwidth
ON Response
Insertion
Loss
“OFF” Switch drain capacitance. Measured
with reference to ground.
“ON” Switch capacitance. Measured with
reference to ground.
Digital input capacitance
Delay time measured between the 50% and
90% points of the digital inputs and the switch
“ON” condition when switching from one
address state to another
Delay time between the 50% and 90% points
of the EN digital input and the Switch “ON”
condition
Delay time between the 50% and 90% points
of the EN digital input and the Switch “OFF”
condition
“OFF” Time measured between the 80% points
of both switches when switching from one
address state to another
Measure of the glitch impulse transferred from
the digital input to the analog output during
switching
Measure of unwanted signal coupling through
an “OFF” switch
Measure of unwanted signal that is coupled
through from one channel to another as a result
of parasitic capacitance
Frequency at which the output is attenuated
by 3 dB
Frequency response of the “ON” Switch
Loss due to the ON Resistance of
the switch
–6–
REV. B
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