CDP68HC68T1E(1997) 데이터 시트보기 (PDF) - Intersil

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CDP68HC68T1E
(Rev.:1997)

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

Intersil 

Functional Block Diagram

CE

LINE

XTAL IN

XTAL OUT

VBATT

CLOCK

OUT

INT

VDD

VSS

50/60Hz

OSCILLATOR

FREEZE

CIRCUIT

PRESCALE

SECOND

PRESCALE

SELECT

CLOCK

SELECT

CLOCK

AND

INT

LOGIC

CLOCK

CONTROL

REGISTER

INTERRUPT

CONTROL

REGISTER

LINE

VSYS

POR

PSE

CPUR

SCK

MISO

MOSI

POWER

SENSE

CONTROL

INT STATUS

REGISTER

SERIAL

INTERFACE

AM - PM AND

HOUR LOGIC

MINUTE

HOUR

CALENDAR

LOGIC

DAY/DAY

OF WEEK

8-BIT DATA BUS

SECOND

LATCH

COMPARATOR

MINUTE

LATCH

HOUR

LATCH

32 X 8

RAM

FIGURE 1. REAL TIME CLOCK FUNCTIONAL DIAGRAM

MONTH

YEAR

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