T80C5112 데이터 시트보기 (PDF) - Atmel Corporation

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T80C5112

8-bit Microcontroller with A/D converter

Atmel Corporation 

6.3. Functional Block diagram

T80C5112

XT_SP

ResetB

Ckrl

Reload

Xtal1

Xtal2

Xtal_Osc

OSCA

OSCAEN

OSCBEN

PwdOsc

RC_Osc

OSCB

PwdRC

1

Mux OscOut

+

8-bit

Filter

Prescaler-Divider

0

0

1

CKS

X2

RCLF_Osc

OSCC

RCLF_OFF

OSCBEN

OSCAEN

Timer 0 clock

:128

Sub Clock

1

0

RCLF_OFF

1

CkOut

0

WD clock

A/D clock

CkAdc

Peripherals clock

CkIdle

Cpu clock

Ck

Quiet Pwd Idle

Figure 1. Functional block diagram

6.4. Operating modes

6.4.1. Reset :

· An hardware RESET select Xtal_Osc or RC_Osc depending on the RST_OSC configuration bit

6.4.2. Functional modes :

6.4.2.1. NORMAL MODES :

· CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL

registers

· CKS bit selects either Xtal_Osc or RC_Osc

· CKRL register determines the frequency of the selected clock, unless X2 bit is set.

In this case the prescaler/divider is not used, so CPU core needs only 6-clock period per machine cycle.

According to the value of the peripheral X2 individual bit, each peripherals need 6 or 12 clock period per

instructions.

· It is always possible to switch dynamicaly by software from Xtal_Osc to RC_Osc, and vice versa by changing

CKS bit, a synchronization cell allowing to avoid any spike during transition.

Rev. B - November 10, 2000

9

Preliminary

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