STW5095(2005) 데이터 시트보기 (PDF) - STMicroelectronics

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STW5095
(Rev.:2005)

Low Power Asynchronous Stereo Audio Codec with Integrated Power Amplifiers

STMicroelectronics 

STw5095

3 Functional Description

Device Programming: I2C. The I2C Control Interface timing is shown in Section 5.1 on page

41. The interface has an internal counter that keeps the current address of the control register

to be read or written. At each write access of the interface the address counter is loaded with

the data of the register address field. The value in the address counter is increased after each

data byte read or write. It is possible to access the interface in 2 modes: single-byte mode in

which the address and data of a single register are specified, and multi-byte mode in which the

address of the first register to be written or read is specified and all the following bytes

exchanged are the data of successive registers starting from the one specified (in multi-byte

mode the internal address counter restart from register 0 after the last register 36). Using the

multi-byte mode it is possible to write or read all the registers with a single access to the device

on the I2C bus.

Device Programming: SPI. The SPI Control Interface timing is shown in Section 5.2 on page

42. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin selection for serial data out

(none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in CR33 selects the high impedance

state of serial data out pin when idle. The first bit sent on SDIN, after CSB falling edge, sets the

interface for writing (SDIN=1) or reading (SDIN=0), then a 7-bit Control Register address

follows.

If the interface is set for writing then the last 8 bits on SDIN are written in the control register.

If the interface is set for reading then after the 7 bit address STw5095 sends out 8 bits data on

the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored. If

SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful to

clear the IRQ event bits in CR32.

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