Philips Semiconductors
Octal buffer/driver with parity, non-inverting (3-State)
Product specification
74F456
FEATURES
• High impedance NPN base inputs for reduced loading
(40µA in High and Low states)
• 74F456 combines 74F244 and 74F280A functions in one package
• 74F456 is a center pin version of the 74F656A
• Non-Inverting
• 3-State outputs sink 64mA and source 15mA
• 24-pin plastic Slim DIP (300 mil) package
• Broadside pinout simplifies PC board layout
DESCRIPTION
The 74F456 is an octal buffer and line driver with parity
generation/checking designed to be employed as memory address
drivers, clock drivers and bus-oriented transmitters/receivers. These
parts include parity generator/checker to improve PC board density.
TYPE
74F456
TYPICAL
PROPAGATION
DELAY
7.5ns
TYPICAL SUPPLY CURRENT
(TOTAL)
64mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
24-pin plastic Slim
DIP (300mil)
N74F456N
24-pin plastic SOL
N74F456D
PKG DWG #
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
D0–D7
Data inputs
2.0/0.066
PI
Parity input
1.0/0.033
OE0, OE1
Output Enable inputs (active Low)
1.0/0.033
ΣE, ΣO
Parity outputs
750/106.7
Q0–Q7
Data outputs
750/106.7
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as 20µA in the High state and 0.6mA in the Low state.
PIN CONFIGURATION
LOGIC SYMBOL
LOAD VALUE
HIGH/LOW
40µA/40µA
20µA/20µA
20µA/20µA
15mA/64mA
15mA/64mA
OE0 1
OE1 2
PI 3
D0 4
D1 5
D2 6
VCC 7
D3 8
D4 9
D5 10
D6 11
D7 12
24 ΣO
23 ΣE
22 Q0
21 Q1
20 Q2
19 GND
18 GND
17 Q3
16 Q4
15 Q5
14 Q6
13 Q7
4 5 6 8 9 10 11 12
D0 D1 D2 D3 D4 D5 D6 D7
3
PI
1
OE0
2
OE1
ΣE
23
ΣO
24
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 7
22 21 20 17 16 15 14 13
GND = Pin 18, 19
SF00960
SF00958
2000 Aug 01
2
853–0371 24250