STB18N65M5, STD18N65M5
Test circuits
3
Test circuits
Figure 16. Test circuit for resistive load switching times
VGS
pulse width
VD
RG
RL
2200
+ μF
3.3
μF
VDD
D.U.T.
AM01468v1
Figure 18. Test circuit for inductive load switching and
diode recovery times
Figure 17. Test circuit for gate charge behavior
VGS
pulse width
+
2200
μF
1 kΩ
12 V
47 kΩ
100 nF
VDD
1 kΩ
IG= CONST
2.7 kΩ
47 kΩ
100 Ω
D.U.T.
VG
AM01469v1
Figure 19. Unclamped inductive load test circuit
A
D
AA
G
D.U.T.
fast
diode
100 µH
S
B
25 Ω
BB
D
3.3
µF
1000
+ µF
VDD
G
D.U.T.
+ RG
S
_
AM01470v1
Figure 20. Unclamped inductive waveform
V(BR)DSS
VD
VDD
IDM
ID
VDD
AM01472v1
L
VD
2200
+ µF
3.3
µF
VDD
ID
Vi
pulse width
D.U.T.
AM01471v1
Figure 21. Switching time waveform
Id
90%Vds
Concept waveform for Inductive Load Turn-off
90%Id
Vgs
90%Vgs on
10%Vds
Vgs(I(t ))
Vds
Tdelay -off
Trise
Tfall
Tcross -over
10%Id
AM05540v2
DS9171 - Rev 2
page 8/23