STA333BWQS 데이터 시트보기 (PDF) - STMicroelectronics

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STA333BWQS

2.1-channel high-efficiency digital audio system with QSound QHD®

STMicroelectronics 

Electrical specifications

3.5

Power-on sequence

Figure 3. Power-on sequence

VCC

VDD_DIG

XTI

Reset

Don’t care

TR

TC

I2C

PWDN

Don’t care

STA333BWQS

CMD0 CMD1 CMD2

Note:

Note:

Referring to Figure 3 above:

TR = mimimum time between XTI master clock stable and reset removal: 1 ms,

TC = minimum time between reset removal and I2C program sequence start: 1 ms.

Clock stable means: fmax - fmin < 1 MHz.

VCC > VDD_DIG must be guaranteed at all times.

3.6

3.6.1

Testing

Functional pin status

Table 8. Functional pin status

Pin name Number Logic value

IC status

PWRDN

23

0

Low-power mode

PWRDN

23

TWARN

20

1

Normal operation

0

Temperature warning from external power stage

TWARN

20

1

Normal operation

EAPD

19

0

Low-power operation for power stage. All internal regulators

are switched off

EAPD

19

1

Normal operation

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