STA323WTR 데이터 시트보기 (PDF) - STMicroelectronics
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STA323WTR Datasheet PDF : 41 Pages
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STA323W
Table 12. DDX® Output Modes
OM (1,0)
00
01
10
11
Output Stage – Mode
Not Used
Not Used
DDX-2060/2100/2160
Variable Compensation
7.4.2 5.3.2DDX® Variable Compensating Pulse Size
The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact
Apogee applications for support when deciding this function.
Table 13. DDX® Compensating Pulse
CSZ (4…0)
00000
00001
…
10000
…
11111
Compensating Pulse Size
0 Clock period Compensating Pulse Size
1 Clock period Compensating Pulse Size
…
16 Clock period Compensating Pulse Size
…
31 Clock period Compensating Pulse Size
7.5 Configuration Register D (Address 03h)
D7
D6
D5
D4
D3
MME
ZDE
DRC
BQL
PSL
0
0
0
0
0
D2
DSPB
0
D1
DEMP
0
D0
HPB
0
7.5.1 High-Pass Filter Bypass
BIT
R/W
RST
NAME
DESCRIPTION
0
R/W
0
HPB High-Pass Filter Bypass Bit.
0 – AC Coupling High Pass Filter Enabled
1 – AC Coupling High Pass Filter Disabled
The STA323W features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of
this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker
damage.
7.5.2 De-Emphasis
BIT
R/W
RST
NAME
DESCRIPTION
1
R/W
0
DEMP
De-emphasis:
0 – No De-emphasis
1 – De-emphasis
By setting this bit to HIGH, or one (1), de-emphasis will implemented on all channels. DSPB (DSP Bypass,
Bit D2, CFA) bit must be set to 0 for De-emphasis to function.
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