Pin description
ST72682
Table 2.
Pin
LQFP64
64
63
45
44
33
32
18
19
54
53
17
Table 3.
Pin
LQFP64
Power supply pins
Pin name
Description
VSS_1
VDD33_1
VSS_2
VDD33_2
VSS_3
VDD33_3
VSS_4
VDD33_4
VSS_5
VDD33_5
VDDOUSB
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
O USB2 PHY, OSC and PLL power supply output (1.8V)
Control and system
Pin name
Level
Description
41
Table 4.
Pin
LQFP64
16
15
14
13
12
11
10
9
RESET
I/O 3.3 CT
USB 2.0 Interface
Reset input with filter with internal pull-up
Pin name
Description
VDDBL
VSSBL
USBDM
USBDP
VDD3
VDDC
VSSC
RREF
S Supply voltage for buffers and deserialisation flip flops (1.8 V)
S Ground for buffers and deserialisation flip flops (1.8 V)
I/O USB2 DATA -
I/O USB2 DATA +
S Supply voltage for the FS compliance (3.3 V)
S Supply voltage for DLL & XOR tree (1.8 V)
S Ground for DLL & XOR tree (1.8 V)
I/O
Ref. resistor for integrated impedance process adaptation
(11.3 kOhms 1% Pull Down)
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