SST29EE010A-250-4I-P 데이터 시트보기 (PDF) - Silicon Storage Technology
부품명
상세내역
제조사
SST29EE010A-250-4I-P Datasheet PDF : 26 Pages
| |||
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
Write
The Page Write to the SST29EE010A/29LE010A/
29VE010A uses the JEDEC Standard Software Data
Protection (SDP) three-byte command sequence.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE010A/29LE010A/29VE010A. Steps 1 and 2
use the same timing for both operations. Step 3 is an
internally controlled write cycle for writing the data loaded
in the page buffer into the memory array for nonvolatile
storage. During both the SDP three-byte load sequence
and the byte-load cycle, the addresses are latched by the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched by the rising edge of either CE# or
WE#, whichever occurs first. The internal write cycle is
initiated by the TBLCO timer after the rising edge of WE#
or CE#, whichever occurs first. The write cycle, once
initiated, will continue to completion, typically within 5 ms.
See Figures 4 and 5 for WE# and CE# controlled page
write cycle timing diagrams and Figures 13 and 15 for
flowcharts.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three-byte load se-
quence that allows writing to the selected page and will
leave the SST29EE010A/29LE010A/29VE010A pro-
tected at the end of the Page Write. The page load cycle
consists of loading 1 to 128 bytes of data into the page
buffer. The internal write cycle consists of the TBLCO
time-out and the write timer operation. During the Write
operation, the only valid reads are Data# Polling and
Toggle Bit.
The Page Write operation allows the loading of up to 128
bytes of data into the page buffer of the SST29EE010A/
29LE010A/29VE010A before the initiation of the internal
write cycle. During the internal write cycle, all the data in
the page buffer is written simultaneously into the memory
array. Hence, the page write feature of SST29EE010A/
29LE010A/29VE010A allow the entire memory to be
written in as little as 5 seconds. During the internal write
cycle, the host is free to perform additional tasks, such as
to fetch data from other locations in the system to set up
the write to the next page. In each Page Write operation,
all the bytes that are loaded into the page buffer must
have the same page address, i.e. A7 through A16. Any
byte not loaded with user data will be written to FF.
See Figures 4 and 5 for the page write cycle timing
diagrams. If after the completion of the three-byte SDP
load sequence the host loads a byte into the page buffer
within a byte-load cycle time (TBLC) of 100 µs, the
SST29EE010A/29LE010A/29VE010A will stay in the
page load cycle. Additional bytes are then loaded con-
secutively. The page load cycle will be terminated if no
additional byte is loaded into the page buffer within 200
µs (TBLCO) from the last byte-load cycle, i.e., no sub-
sequent WE# or CE# high-to-low transition after the last
rising edge of WE# or CE#. Data in the page buffer can
be changed by a subsequent byte-load cycle. The page
load period can continue indefinitely, as long as the host
continues to load the device within the byte-load cycle
time of 100 µs. The page to be loaded is determined by
the page address of the last byte loaded.
Software Chip Erase
The SST29EE010A/29LE010A/29VE010A provide a
Chip Erase operation, which allows the user to simulta-
neously clear the entire memory array to the “1” state.
This is useful when the entire device must be quickly
erased.
The Software Chip Erase operation is initiated by using
a specific six-byte load sequence. After the load se-
quence, the device enters into an internally timed cycle
similar to the write cycle. During the Erase operation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure 8 for timing diagram, and Figure 17 for
the flowchart.
© 1999 Silicon Storage Technology, Inc.
2
303-01 2/99
Share Link: 