SN74LS165 데이터 시트보기 (PDF) - ON Semiconductor
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SN74LS165 Datasheet PDF : 8 Pages
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10 DS
2 CP1
15 CP2
1 PL
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
SN74LS165
LOGIC DIAGRAM
11
12
13
14
3
4
5
6
P0
P1
P2
P3
P4
P5
P6
P7
PRESET
S Q0
CP
R CLQ0
PRESET
S Q1
CP
R CLQ1
PRESET
S Q2
CP
R CLQ2
PRESET
S Q3
CP
R CLQ3
PRESET
S Q4
CP
R CLQ4
PRESET
S Q5
CP
R CLQ5
PRESET
S Q6
CP
R CLQ6
PRESET
S Q7
9
CP
R CLQ7
7
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
For clock operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clock is HIGH. Otherwise, the rising inhibit signal will cause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
TRUTH TABLE
CP
CONTENTS
PL
1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L X X P0 P1 P2 P3 P4 P5 P6 P7
HL
DS Q0 Q1 Q2 Q3 Q4 Q5 Q6
HH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
H
L DS Q0 Q1 Q2 Q3 Q4 Q5 Q6
H
H Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
RESPONSE
Parallel Entry
Right Shift
No Change
Right Shift
No Change
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