HIP6028EVAL1 데이터 시트보기 (PDF) - Intersil

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HIP6028EVAL1

Advanced PWM and Dual Linear Power Control with Integrated ACPI Support Interface

Intersil 

HIP6028

+5VIN

+3.3VIN

CIN

Q3

VOUT3

VOUT2

+12V

CVCC

COCSET

VCC GND

VIN2

OCSET

ROCSET

UGATE Q1

DRIVE3

PHASE

HIP6028

Q2

VOUT2 LGATE

LOUT1 VOUT1

COUT1

CR1

SS PGND

CSS

COUT2 KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 11. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

A multi-layer printed circuit board is recommended. Figure 11

shows the connections of the critical components in the

converter. Note that capacitors CIN and COUT could each

represent numerous physical capacitors. Dedicate one solid

layer for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into

smaller islands of common voltage levels. The power plane

should support the input power and output power nodes.

Use copper filled polygons on the top and bottom circuit

layers for the phase nodes. Use the remaining printed circuit

layers for small signal wiring. The wiring traces from the

control IC to the MOSFET gate and source should be sized

to carry 1A currents. The traces for VOUT2 need only be

sized for 0.2A. Locate COUT2 close to the HIP6028 IC.

PWM Controller Feedback Compensation

Both PWM controllers use voltage-mode control for output

regulation. This section highlights the design consideration

for a voltage-mode controller. Apply the methods and

considerations to both PWM controllers.

Figure 12 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage is

regulated to the reference voltage level. The reference

voltage level is the DAC output voltage for the PWM

controller. The error amplifier output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse-width

modulated wave with an amplitude of VIN at the PHASE node.

The PWM wave is smoothed by the output filter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

gain and the output filter, with a double pole break frequency

at FLC and a zero at FESR. The DC gain of the modulator is

simply the input voltage, VIN, divided by the peak-to-peak

oscillator voltage, ∆VOSC.

2-321

∆VOSC

OSC

PWM

COMP

-

+

DRIVER

DRIVER

ZFB

VE/A

-

ZIN

+

ERROR

AMP

REFERENCE

VIN

LO

VOUT

PHASE

CO

ESR

(PARASITIC)

DETAILED FEEDBACK COMPENSATION

C2

C1 R2

ZFB

VOUT

ZIN

C3 R3

R1

COMP

-

FB

+

HIP6028

REFERENCE

FIGURE 12. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Modulator Break Frequency Equations

FLC=

-------------------1--------------------

2π × LO × CO

FESR= -2---π-----×-----E----S--1---R------×-----C----O---

The compensation network consists of the error amplifier

internal to the HIP6028 and the impedance networks ZIN

and ZFB. The goal of the compensation network is to provide

a closed loop transfer function with an acceptable 0dB

crossing frequency (f0dB) and adequate phase margin.

Phase margin is the difference between the closed loop

phase at f0dB and 180 degrees. The equations below relate

the compensation network’s poles, zeros and gain to the

components (R1, R2, R3, C1, C2, and C3) in Figure 12.

Use these guidelines for locating the poles and zeros of the

compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)

3. Place 2ND Zero at Filter’s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

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