CD3206BB 데이터 시트보기 (PDF) - Philips Electronics
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CD3206BB Datasheet PDF : 18 Pages
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Philips Semiconductors
9-bit latched/registered/pass-thru Futurebus+ transceiver
Product specification
FB2031
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
VBIASV Bias pin voltage
IBIASV Bias pin DC current
VBn
ILM
IHM
IBnPEAK
Bus voltage during prebias
Fall current during prebias
Rise current during prebias
Peak bus current during
insertion
IOLOFF Power up current
tGR Input glitch rejection
VCC = 0 to 5.25V, Bn = 0 to 2.0V
VCC = 0 to 4.75V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
VCC = 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
B0 – B8 = 0V, Bias V = 5.0V
B0 – B8 = 2V, Bias V = 4.5 to 5.5V
B0 – B8 = 1V, Bias V = 4.5 to 5.5V
VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns
VCC = 0 to 5.25V, OEB0 = 0.8V
VCC = 0 to 2.2V, OEB0 = 0 to 5V
VCC = 5.0V
LIMITS
MIN
NOM
MAX
4.5
5.5
1
10
1.62
2.1
1
-1
10
100
100
1.35
1.0
UNIT
V
mA
µA
V
µA
µA
mA
µA
ns
AC ELECTRICAL CHARACTERISTICS (Industrial)
SYMBOL
PARAMETER
TEST
CONDITION
A PORT LIMITS
Tamb = +25°C, VCC = 5V,
CL = 50pF, RL = 500Ω
Tamb = –40 to +85°C,
VCC = 5V±10%,
CL = 50pF, RL = 500Ω
MIN TYP MAX
MIN
MAX
UNIT
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tTLH
tTHL
tSK(o)
tSK(p)
Maximum clock frequency
Propagation delay (thru mode)
Bn to An
Propagation delay (transparent latch)
Bn to An
Propagation delay
LCBA to An
Propagation delay
SEL0 or SEL1 to An
Output enable time from High or Low
OEA to An
Output disable time to High or Low
OEA to An
Output transition time, An Port
10% to 90%, 90% to 10%
Output to output skew for multiple
channels1
Pulse skew 2
tPHL – tPLH MAX
Waveform 4
120 150
100
Waveform 1, 2
2.5
4.4
5.9
2.4
4.2
5.5
2.3
2.4
Waveform 1, 2
2.9
4.6
6.2
2.8
4.3
5.9
2.7
2.5
Waveform 1, 2
2.6
4.1
5.5
2.4
4.7
6.1
2.0
2.0
Waveform 1, 2
1.5
3.8
5.2
1.7
3.9
6.0
1.2
1.5
Waveform 5, 6
2.1
3.5
4.8
2.0
3.8
5.3
1.8
1.7
Waveform 5, 6
1.9
3.4
4.8
1.7
3.2
4.8
1.6
1.5
Test Circuit and
3.0
Waveforms
1.7
Waveform 3
0.5
1.0
Waveform 2
0.5
1.0
MHz
7.0
6.2
ns
7.1
7.0
ns
6.2
6.8
ns
6.2
6.5
ns
6.0
6.3
ns
5.5
5.5
ns
7.5
4.0
ns
1.5
ns
1.0
ns
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally.
6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
1995 May 25
9
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