S25FL064K0SMFI003 데이터 시트보기 (PDF) - Spansion Inc.
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S25FL064K0SMFI003
Spansion Inc.
S25FL064K0SMFI003 Datasheet PDF : 66 Pages
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Data Sheet
8.6
AC Electrical Characteristics
Description
Spec
Symbol
Alt
Unit
Min
Typ
Max
Clock frequency for all instructions, except Read Data
(03h) 2.7V-3.6V VCC and Industrial Temperature
FR
fC
DC
Clock frequency Read Data instruction (03h)
fR
DC
Clock High, Low Time except Read Data (03h)
tCLH, tCLL (1) tCH, tCL
6
Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL (1)
8
Clock Rise Time peak to peak
tCLCH (2)
0.1
Clock Fall Time peak to peak
tCHCL (2)
0.1
CS# Active Setup Time relative to CLK
tSLCH
tCSS
5
CS# Not Active Hold Time relative to CLK
tCHSL
5
Data In Setup Time
tDVCH
tDSU
2
Data In Hold Time
tCHDX
tDH
5
CS# Active Hold Time relative to CLK
tCHSH
5
CS# Not Active Setup Time relative to CLK
tSHCH
5
CS# Deselect Time (for Array Read -> Array Read)
tSHSL1
tCSH
10
CS# Deselect Time (for Erase or Program -> Read
Status Registers)
Volatile Status Register Write Time
tSHSL2
50
tCSH
50
80
MHz
33
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable Time
Clock Low to Output Valid 2.7V-3.6V / 3.0V-3.6V
Clock Low to Output Valid (for Read ID instructions)
2.7V-3.6V / 3.0V-3.6V
tSHQZ (2)
tDIS
tCLQV1
tV1
tCLQV2
tV2
7
ns
7/6
ns
8.5 / 7.5
ns
Output Hold Time
tCLQX
tHO
0
HOLD# Active Setup Time relative to CLK
tHLCH
5
HOLD# Active Hold Time relative to CLK
tCHHH
5
HOLD# Not Active Setup Time relative to CLK
tHHCH
5
HOLD# Not Active Hold Time relative to CLK
tCHHL
5
HOLD# to Output Low-Z
tHHQX (2)
tLZ
HOLD# to Output High-Z
tHLQZ (2)
tHZ
Write Protect Setup Time Before CS# Low
tWHSL (3)
20
Write Protect Hold Time After CS# High
tSHWL (3)
100
CS# High to Power-down Mode
tDP (2)
CS# High to Standby Mode without Electronic Signature
Read
tRES1 (2)
ns
ns
ns
ns
ns
7
ns
12
ns
ns
ns
3
µs
3
µs
CS# High to Standby Mode with Electronic Signature
Read
tRES2 (2)
1.8
µs
CS# High to next Instruction after Suspend
Write Status Register Time
Byte Program Time (First Byte) (4)
Additional Byte Program Time (After First Byte) (4)
Page Program Time
Sector Erase Time (4 kB)
Block Erase Time (32 kB)
Block Erase Time (64 kB)
Chip Erase Time
tSUS (2)
tW
tBP1
tBP2
tPP
tSE
tBE1
tBE2
tCE
20
µs
10
15
ms
30
50
µs
2.5
12
µs
0.7
3
ms
30
200/400(5)
ms
120
800
ms
150
1000
ms
15
30
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.
4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of
bytes programmed.
5. Max Value tSE with <50K cycles is 200 ms and >50K & <100K cycles is 400 ms.
July 13, 2011 S25FL064K_00_03
S25FL064K
61
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