PSB2115 데이터 시트보기 (PDF) - Siemens AG
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PSB2115 Datasheet PDF : 317 Pages
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PSB 2115
PSF 2115
List of Figures
Page
Figure 1: Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2: Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4: ISDN PC Adapter Card for S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5: ISDN PC Adapter Card for U or S interface . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6: ISDN Voice/Data Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7: ISDN Stand-Alone Terminal with POTS interface . . . . . . . . . . . . . . . . . . 30
Figure 8: Multiline PC-Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9: Receive Data Flow of IPAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10: Transmit Data Flow of IPAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11: Location of Time-Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12: NRZ Encoding/NRZI Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13: Data Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14: Contents of RFIFOD (short message) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15: Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16: Contents of RFIFOD (long message) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17: Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18: D-Channel Access Control on TIC Bus and S Bus. . . . . . . . . . . . . . . . . . 54
Figure 19: Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . . . . 63
Figure 20: Intelligent NT-Configuration for IOM-2 Channel Switching. . . . . . . . . . . . 65
Figure 21: Data Path Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 22: S/T -Interface Line Code (without code violation). . . . . . . . . . . . . . . . . . . 69
Figure 23: Frame Structure at Reference Points S and T (ITU I.430) . . . . . . . . . . . . 70
Figure 24: Wiring Configurations in User Premises. . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 25: Connection of the Line Transformers and Power Supply to the IPAC . . . 82
Figure 26: Equivalent Internal Circuits of Receiver and Transmitter Stages . . . . . . . 83
Figure 27: External Circuitry for Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 28: External Circuitry for Symmetrical Receivers . . . . . . . . . . . . . . . . . . . . . . 86
Figure 29: Receiver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 30: Receiver Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 31: Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 32: Clock System of the IPAC in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 33: Clock System of the IPAC in TE and LT-T Modes . . . . . . . . . . . . . . . . . . 91
Figure 34: ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 35: ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 36: Layer 2 Test Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 37: Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 38: High and Low Active Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 39: IPAC Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 40: Timing Diagram for DMA-Transfers (fast) Transmit (n < 64, remainder
of a long message or n = k × 64)
104
Semiconductor Group
9
11.97
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