PEF22554HT/E 데이터 시트보기 (PDF) - Infineon Technologies

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PEF22554HT/E

Quad E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Infineon Technologies 

3

JTAG Ball Names

QuadFALC® V2.1

PEF 22554 HT/E

JTAG Ball Names

Page 52, Chapter 2.2, Pin Definitions and Functions

The BGA ball numbers are missing for the JTAG pins. They are as shown below.

Table 5

Pin Definitions - Miscellaneous

Pin No.

Ball No. Symbol

Input

Output

Supply

Function

Boundary Scan/Joint Test Access Group (JTAG)

131

B6

TRS

I + PU Test Reset for Boundary Scan

(active low). If not connected, an internal

pullup transistor ensures high input level.

If the JTAG boundary scan is not used, this

pin must be connected to RES or VSS.

112

D11

TDI

I + PU Test Data Input for Boundary Scan

If not connected an internal pullup

transistor ensures high input level.

141

D5

TMS

I + PU Test Mode Select for Boundary Scan

If not connected an internal pullup

transistor ensures high input level.

140

C4

TCK

I + PU Test Clock for Boundary Scan

If not connected an internal pullup

transistor ensures high input level.

113

C11

TDO

O

Test Data Output for Boundary Scan

Addendum

4

DS1, 2003-07-02

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