PCA9575 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

NXP Semiconductors. 

NXP Semiconductors

PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7. Functional description

7.1 I/O ports

The 16 I/O ports are organized as two banks of 8 ports each. The system master can

enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits.

The data for each input or output is kept in the corresponding Input or Output register. The

polarity of the read register can be inverted with the Polarity Inversion register. Either a

bus-hold function or pull-up/pull-down feature can be selected by programming

corresponding registers. A bus-hold provides a valid logic level when the I/O bus is not

actively driven. It consists of a pair of buffers, one being weak (low drive-strength), that

latch the input at the last driven value. This prevents the input from floating while it is being

driven by a 3-state output. Latching the last valid logic state of input prevents it from

settling at a midpoint between VDD and ground that in turn consumes power. An active bus

driver can easily override the logic level set by the bus-keeper.

When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or

pull-down by programming the pull-up/pull-down configuration register.

7.2 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). Address configuration for

the device depends on the package type chosen. The device offered in a 24-pin package

will have a fixed slave address for the PCA9575 as shown in Figure 6.

slave address

0 1 0 0 0 0 0 R/W

fixed

002aad567

Fig 6. PCA9575 device address for 24-pin version

The last bit of the first byte defines the operation to be performed. When set to logic 1 a

read is selected, while logic 0 selects a write operation.

The slave address for the 28-pin version of the PCA9575 is shown in Figure 7.

slave address

0 1 0 A3 A2 A1 A0 R/W

fixed

hardware selectable

002aad583

Fig 7. PCA9575 device address for 28-pin version

PCA9575_3

Product data sheet

Rev. 03 — 9 November 2009

© NXP B.V. 2009. All rights reserved.

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