Unit Loading/Fan Out
Pin Names
Description
P0–P7
PE
U/D
CEP
CET
CP
TC
Q0–Q7
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Input
Terminal Count Output (Active LOW)
Flip-Flop Outputs
Logic Diagram
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
5.0/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
www.fairchildsemi.com
2