NJW4351
PIN/ CIRCUIT OPERATIONAL DEFINITION
♦ Logic Input Pins Operational Voltage Definition
VIN
VDD
2.0V
H level input voltage
At VDD=3.3V
V
5.0V
2.0V
∆VHYS
H level input voltage
0.8V
0V
L level input voltage
0.8V
0V
L level H level
L level input voltage
L lebvel H level L level
♦ Logic Input Pins Timing Definition
At VDD=3.3V
Master Pin
STEP
V
VIH=2.0V
VIL=0.8V
tp
tp
Slave Pins
HSM, DIR
RESET, PD
VIH=2.0V
tp
tp
VIL=0.8V
tDS1
tDH2
tDS2
tDH1
t
Data Setup Time and Data Hold Time are defined to positive edge of STEP.
tDS1,tDS2=Data Setup Time, tDH1,tDH2=Data Hold Time
tDS1,tDH1=HSM,DIR,RESET, PD, tDS2,tDH2=HSM,DIR
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