NCP1611 데이터 시트보기 (PDF) - ON Semiconductor

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NCP1611

Enhanced, High-Efficiency Power Factor Controller

ON Semiconductor 

NCP1611

VSEBNOSpEinpin

V to I

IBO

IREGUL

IBO

converter

VCVOcNoTnRtrOolLppinin

Multiplier

LLine

FFFcFoconnttrroollppinin

V to I

converter

IREGUL

. IREGUL= K VREGUL

. . Km IREGUL IBO

SSUUMM

+

RRAAMMPP

RFF

0.75 V / 0.651V

pfpcfOcOKK

SskKipIP2

Figure 61. Generation of the Current Information

Skip Mode

As illustrated in Figure 61, the circuit also skips cycles

near the line zero crossing where the current is very low. A

comparator monitors the pin 3 voltage (“FFcontrol”

voltage) and inhibits the drive when Vpin3 is lower than a

0.65 V internal reference. Switching resumes when Vpin3

exceeds 0.75 V (0.1 V hysteresis). This inhibits circuit

operation when the power transfer is particularly inefficient

at the expense of slightly increased current distortion. When

superior power factor is needed, this function can be

inhibited offsetting the “FFcontrol” pin by 0.75 V. The skip

mode capability is disabled whenever the PFC stage is not

in nominal operation (as dictated by the “pfcOK” signal −

see block diagram and “pfcOK Internal Signal” Section).

The circuit does not abruptly interrupt the switching when

Vpin3 goes below 0.65 V. Instead, the signal VTON that

controls the on−time is gradually decreased by grounding

the VREGUL signal applied to the VTON processing block (see

Figure 9). Doing so, the on−time smoothly decays to zero in

three to four switching periods typically. Figure 62 shows

the practical implementation.

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