MT9046(2003) 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

부품명

상세내역

제조사

MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

Data Sheet

MT9046

reference switch or a mode change. The observation period is usually the time from the disturbance, to just

after the synchronizer has settled to a steady state.

In the case of the MT9046, the output signal phase continuity is maintained to within ±5ns at the instance (over

one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or

type of mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase

shift is limited to a maximum phase slope of approximately 5ns/125us. This meets the AT&T TR62411 maximum

phase slope requirement of 7.6ns/125us and Bellcore GR-1244-CORE (81ns/1.326ms).

Phase Lock Time

This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input

signal and output signal are not changing in phase with respect to each other (not including jitter).

Lock time is very difficult to determine because it is affected by many factors which include:

• initial input to output phase difference

• initial input to output frequency difference

• synchronizer loop filter

• synchronizer limiter

Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer

requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter

which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times.

The MT9046 loop filter and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope

requirements. Consequently, phase lock time, which is not a standards requirement, may be longer than in

other applications. See AC Electrical Characteristics - Performance for Maximum Phase Lock TIme.

MT9046 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming

reference within approximately 500 ms.

MT9046 Measures of Performance

The following are some synchronizer performance indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter

may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by

measuring the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters

depending on the applicable standards. In the MT9046, the intrinsic Jitter is limited to less than 0.02UI on the

2.048 MHz and 1.544 MHz clocks.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in

the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The

applied jitter magnitude and jitter frequency depends on the applicable standards.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of

jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is

measured with various filters depending on the applicable standards.

For the MT9046, two internal elements determine the jitter attenuation. This includes the internal 1.9Hz low

pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125us.

Zarlink Semiconductor Inc.

13

Share Link: