MPC9608 데이터 시트보기 (PDF) - Motorola => Freescale

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MPC9608

1:10 LVCMOS Zero Delay Clock Buffer

Motorola => Freescale 

MPC9608

Freescale Semiconductor, Inc.

3.0

OutA

2.5

tD = 3.8956

2.0

In

1.5

OutB

tD = 3.9386

1.0

0.5

0

2

4

6

8 10 12 14

TIME (nS)

Figure 6. Single versus Dual Waveforms

Since this step is well above the threshold region, it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 7 “Optimized Dual Line Termination” should be used.

In this case the series terminating resistors are reduced such

that when the parallel combination is added to the output buffer

impedance the line impedance is perfectly matched.

MPC9608

OUTPUT

BUFFER

14 Ω

RS = 22 Ω ZO = 50 Ω

RS = 22 Ω ZO = 50 Ω

14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω

25 Ω = 25 Ω

Figure 7. Optimized Dual Line Termination

Pulse

Generator

Z = 50 Ω

MPC9608 DUT

ZO = 50 Ω

ZO = 50 Ω

RT = 50 Ω

VTT

RT = 50 Ω

VTT

Figure 8. CCLK MPC9608 AC test reference for VCC = 3.3 V

8

For More Information On This Product,

TIMING SOLUTIONS

Go to: www.freescale.com

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