MPC9446 데이터 시트보기 (PDF) - Motorola => Freescale
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MPC9446
Motorola => Freescale
MPC9446 Datasheet PDF : 12 Pages
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MPC9446
Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
VIL
VOH
VOL
ZOUT
IIN
ICCQc
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Currentb
Maximum Quiescent Supply Current
1.7
VCC + 0.3
V
LVCMOS
-0.3
0.7
V
LVCMOS
1.8
V
IOH=-15 mAa
0.6
V
IOL= 15 mA
17 - 20b
W
±200
µA VIN=GND or VIN=VCC
2.0
mA All VCC Pins
a. The MPC9446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
b. Input pull-up / pull-down resistors influence input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)a b
Symbol
fref
fMAX
Characteristics
Input Frequency
Maximum Output Frequency
Min
0
÷1 output
0
÷2 output
0
Typ
Max
Unit
250c
MHz
250b
125
MHz
MHz
tP, REF Reference Input Pulse Width
1.4
tr, tf
CCLK Input Rise/Fall Time
tPLH
tPHL
Propagation delay
CCLK0,1 to any Q
2.6
CCLK0,1 to any Q
2.6
tPLZ, HZ Output Disable Time
tPZL, LZ Output Enable Time
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
ns
1.0d
ns
5.6
ns
5.5
ns
10
ns
10
ns
150
ps
200
ps
350
ps
tsk(PP)
tSK(P)
Device-to-device Skew
Output pulse skewe
3.0
ns
200
ps
Condition
FSELx=0
FSELx=1
0.7 to 1.7V
DCQ
Output Duty Cycle
÷1 or ÷2 output
45
50
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns 0.6 to 1.8V
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. AC specifications are design targets, final specification is pending device characterization.
c. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%,
TA = –40°C to +85°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
ps
250
ps
350
ps
tsk(PP)
tPLH,HL
tSK(P)
Device-to-device Skew
Propagation delay
Output pulse skewc
CCLK0,1 to any Q
2.5
ns
See 3.3V table
250
ps
DCQ
Output Duty Cycle
÷1 or ÷2 output
45
50
55
%
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
c. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Condition
DCREF = 50%
TIMING SOLUTIONS
5
MOTOROLA
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