MPC9352
CCLK
FB_IN
PLL_EN
F_RANGE
FSELA
FSELB
FSELC
MR/OE
Freescale Semiconductor, Inc.
CCLK
1
÷2
1
÷6
Bank A
1
QA0
Ref
QA1
VCO 0
PLL
0
÷4
0
QA2
FB
÷2
QA3
QA4
Bank B
QB0
1
QB1
0
QB2
QB3
1 Bank C
QC0
0
QC1
(all input resistors have a value of 25kW)
Figure 1. MPC9352 Logic Diagram
24 23 22 21 20 19 18 17
VCC
25
16
VCC
QB2
26
15
QA2
QB3
27
14
QA1
GND
28
GND
29
MPC9352
13
GND
12
QA0
QC0
30
11
VCC
QC1
31
10
VCCA
VCC
32
9
PLL_EN
12345678
It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see application section for details.
Figure 2. MPC9352 32–Lead Package Pinout (Top View)
MOTOROLA
2
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TIMING SOLUTIONS