MPC9330
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36Ω || 36Ω
R0 = 14Ω
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
1. Final skew data pending specification.
3.0
OutA
2.5
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
0.5
0
2
4
6
8
10 12 14
TIME (nS)
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 6. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
MPC9330
OUTPUT
BUFFER
RS = 22Ω ZO = 50Ω
14Ω
RS = 22Ω ZO = 50Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
Pulse
W Generator
Z = 50
ZO = 50Ω
MPC9330 DUT
RT = 50Ω
VTT
ZO = 50Ω
RT = 50Ω
VTT
Figure 7. CCLK MPC9330 AC test reference for Vcc = 3.3V and Vcc = 2.5V
MOTOROLA
10
TIMING SOLUTIONS