MH32S72APHB-6 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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MH32S72APHB-6

2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32S72APHB -6,-7,-8

2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM

[ Read Interrupted by Precharge ]

A burst read operation can be interrupted by precharge of the same bank . Read to PRE

interval is minimum 1 CK. A PRE command output disable latency is equivalent to the

/CAS Latency.

Read Interrupted by Precharge (BL=4)

CL=3

CK

Command

DQ

Command

DQ

Command

DQ

READ

PRE

READ

Q0 Q1 Q2

PRE

READ PRE

Q0 Q1

Q0

CL=2

Command

DQ

Command

DQ

Command

DQ

READ

PRE

Q0 Q1 Q2

READ

PRE

Q0 Q1

READ PRE

Q0

MIT-DS-0380-0.1

MITSUBISHI

ELECTRIC

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17.Mar.2000

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