MCP3204/3208
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and
fCLK = 20*fSAMPLE, unless otherwise noted.
PARAMETER
SYMBOL MIN. TYP. MAX. UNITS
CONDITIONS
Analog Inputs (Continued)
Switch Resistance
1K
Ω See Figure 4-1
Sample Capacitor
20
pF See Figure 4-1
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
0.7 VDD
V
Low Level Input Voltage
VIL
0.3 VDD
V
High Level Output Voltage
VOH
4.1
V IOH = -1mA, VDD = 4.5V
Low Level Output Voltage
VOL
0.4
V IOL = 1mA, VDD = 4.5V
Input Leakage Current
ILI
-10
10
µA VIN = VSS or VDD
Output Leakage Current
ILO
-10
10
µA VOUT = VSS or VDD
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters
CIN, COUT
10
pF VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Clock Frequency
Clock High Time
fCLK
tHI
250
2.0
MHz VDD = 5V (Note 3)
1.0
MHz VDD = 2.7V (Note 3)
ns
Clock Low Time
tLO
250
ns
CS Fall To First Rising CLK
tSUCS
100
ns
Edge
Data Input Setup Time
tSU
50
ns
Data Input Hold Time
tHD
50
ns
CLK Fall To Output Data Valid
tDO
200
ns See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
200
ns See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
100
ns See Test Circuits, Figure 1-2
CS Disable Time
tCSH
500
ns
DOUT Rise Time
tR
100
ns See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
100
ns See Test Circuits, Figure 1-2
(Note 1)
Power Requirements
Operating Voltage
VDD
2.7
5.5
V
Operating Current
Standby Current
IDD
320 400
µA VDD = VREF = 5V, DOUT unloaded
225
VDD = VREF = 2.7V, DOUT unloaded
IDDS
0.5
2
µA CS = VDD = 5.0V
Note 1:
Note 2:
Note 3:
This parameter is guaranteed by characterization and not 100% tested.
See graphs that relate linearity performance to VREF levels.
Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
© 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 3